1. Field of the Invention
The present invention relates to the field of nonvolatile electrically alterable MOS memory devices. More particularly, the invention relates to those memory devices employing MOS floating gate structures useful in MOS and CMOS memory arrays, and the process technology for fabricating such arrays.
2. The Prior Art
Metallic oxide semiconductor (MOS) memory devices utilizing floating gates are commonly employed in integrated electrically programmable read only memory (EPROM) and electrically eraseable read only memory (EEROM) products. The presence or absence of charge on the floating gate of the memory device utilized therein alters the threshold voltage of the device, and the presence or absence of current flow in the channel of the memory device provides a suitable binary indicia for this purpose.
More specifically, thin tunnel dielectric floating gate memory devices are also known in the art. In such devices, charge carriers are transported into and out of the floating gates through a relatively thin portion of the dielectric material located between the floating gate and the device substrate via avalanche injection or Fowler-Nordheim tunneling phenomena. Examples of such devices are given in U.S. Pat. No. 4,019,197 to Lohstroh et al., U.S. Pat. No. 4,115,194 to Harari, and U.S. Pat. No. 4,203,158 to Frohman-Benchkowsky.
These prior art devices have seen use in EEROM arrays, and have taught the use of a thin portion of the dielectric material separating the floating gate from an area in the device substrate which may be located either inside or outside of the channel region of the memory device, through which the charge transport mechanism is realized.
Current trends in both MOS and CMOS technology have been characterized by attempts to scale the geometries of device structures to increasingly smaller sizes, and to provide products to a user which require the external application of but a single power supply voltage (typically 5VDC), and the concomitant generation of the higher programming voltages utilized for floating gate memory devices (typically on the order of from 15 to 25 VDC) in circuitry disposed on the same silicon "chip"0 as the memory array which it serves.
As the MOS and CMOS technology is scaled down to smaller device sizes, thinner dielectric layers, and narrower channel widths, an increasing number of problems arise in the design and large scale fabrication of commercially-viable EEROM products, including the criticality of certain alignments and dimensions of and among the various layers comprising a completed memory cell. For the purposes of this disclosure, a memory cell is a basic unit which may be duplicated a desired number of times to be integrated with appropriate peripheral circuitry to form a memory array and includes at least a memory device and a select device. The criticality of these smaller dimensions and of the mask-to-mask alignment tolerances which must be observed in order to optimally place the topological features of the various layers of these devices relative to one another manifests itself in the high-volume production of memory array products. The ability to reproduce critical dimensions and tolerances directly affects the yield of good parts, and hence, the economic feasibility of large-scale manufacture of memory arrays.
For example, the location of the source and drain regions of the memory device, and the location of the channel of that device with respect to the floating gate is a parameter which can affect functional characteristics of the device. In addition, the alignment of the floating gate with respect to the control gate of a memory device of this type may be important. See, e.g., U.S. Pat. No. 4,142,926 to Morgan. It has also been found that the implanted region in the substrate underlying the portion of the floating gate through which device programming and erasing occurs via the Fowler-Nordheim tunneling phenomenon must be preferentially placed with respect to topological features of later-deposited layers in a manner which assures optimum operating characteristics in the finished device and results in sufficient yields to allow large scale manufacture and sale of products embodying these memory cells.
Thus, despite the obvious advantages provided by the prior art floating gate storage devices, room for improvement of these prior art approaches remains. As a result of some of these problems which exist with current floating gate memory devices, the art has not been able to fully realize the benefits of this technology, especially where prior art techniques are applied to the shrinking geometries of today's more dense memory arrays.